Uncertainty Management of Intelligent Feature Selection in Wireless Sensor Networks

Wireless sensor networks (WSN) are envisioned to revolutionize the paradigm of monitoring complex real-world systems at a very high resolution. However, the deployment of a large number of unattended sensor nodes in hostile environments, frequent changes of environment dynamics, and severe resource constraints pose uncertainties and limit the potential use of WSN in complex real-world applications. Although uncertainty management in Artificial Intelligence (AI) is well developed and well investigated, its implications in wireless sensor environments are inadequately addressed. This dissertation addresses uncertainty management issues of spatio-temporal patterns generated from sensor data. It provides a framework for characterizing spatio-temporal pattern in WSN. Using rough set theory and temporal reasoning a novel formalism has been developed to characterize and quantify the uncertainties in predicting spatio-temporal patterns from sensor data. This research also uncovers the trade-off among the uncertainty measures, which can be used to develop a multi-objective optimization model for real-time decision making in sensor data aggregation and samplin

Design of fault-tolerant optical network.

In this thesis, we have proposed and simulated two fault-tolerant schemes using the De Bruijn graph as a network physical topology where we treat some special nodes as spare resources. In our first scheme, we have attempted to design an all-optical single-hop fault-tolerant network. However, when we tested this scheme by randomly generating faults, it could not provide alternate paths in the presence of faults in most cases. Our second scheme, a hybrid system of single-hop and multihop system can successfully manage multiple faults almost in all cases. However, the disadvantage of our second scheme is that our network is no longer an all-optical network, and its throughput is lower because of electrical buffering at some intermediate points. Another disadvantage of this scheme is that the system can result in intolerable restoration delay for some communications due to the high demand on certain links since there is no upper limit on the number of communications through any edge. We have tried to distribute the communications through different links as uniformly as possible to improve this delay. (Abstract shortened by UMI.) Paper copy at Leddy Library: Theses & Major Papers - Basement, West Bldg. / Call Number: Thesis1999 .M35. Source: Masters Abstracts International, Volume: 39-02, page: 0529. Adviser: Subir Bandyopadhyay. Thesis (M.Sc.)--University of Windsor (Canada), 1999

Design and Validation for FPGA Trust under Hardware Trojan Attacks

Field programmable gate arrays (FPGAs) are being increasingly used in a wide range of critical applications, including industrial, automotive, medical, and military systems. Since FPGA vendors are typically fabless, it is more economical to outsource device production to off-shore facilities. This introduces many opportunities for the insertion of malicious alterations of FPGA devices in the foundry, referred to as hardware Trojan attacks, that can cause logical and physical malfunctions during field operation. The vulnerability of these devices to hardware attacks raises serious security concerns regarding hardware and design assurance. In this paper, we present a taxonomy of FPGA-specific hardware Trojan attacks based on activation and payload characteristics along with Trojan models that can be inserted by an attacker. We also present an efficient Trojan detection method for FPGA based on a combined approach of logic-testing and side-channel analysis. Finally, we propose a novel design approach, referred to as Adapted Triple Modular Redundancy (ATMR), to reliably protect against Trojan circuits of varying forms in FPGA devices. We compare ATMR with the conventional TMR approach. The results demonstrate the advantages of ATMR over TMR with respect to power overhead, while maintaining the same or higher level of security and performances as TMR. Further improvement in overhead associated with ATMR is achieved by exploiting reconfiguration and time-sharing of resources

Secure and Trusted SoC: Challenges and Emerging Solutions

Over the ages, hardware components, platforms and supply chains have been considered secure and trustworthy. However, recent discoveries and reports on security vulnerabilities and attacks in microchips and circuits violate this hardware root of trust. System-on-Chip (SoC) design based on reusable hardware intellectual property (IP) is now a pervasive design practice in the industry due to the dramatic reduction in design/verification cost and time. This growing reliance on reusable pre-verified hardware IPs and a wide array of design automation tools during SoC design, often acquired from untrusted 3rd party vendors, coupled with fabrication in untrusted offshore foundries severely affects the security and trustworthiness of SoCs used in diverse applications. This paper presents an overview of the various security challenges in the SoC design cycle and possible solutions for protection

Secure and Trusted SoC: Challenges and Emerging Solutions

Over the ages, hardware components, platforms and supply chains have been considered secure and trustworthy. However, recent discoveries and reports on security vulnerabilities and attacks in microchips and circuits violate this hardware root of trust. System-on-Chip (SoC) design based on reusable hardware intellectual property (IP) is now a pervasive design practice in the industry due to the dramatic reduction in design/verification cost and time. This growing reliance on reusable pre-verified hardware IPs and a wide array of design automation tools during SoC design, often acquired from untrusted 3rd party vendors, coupled with fabrication in untrusted offshore foundries severely affects the security and trustworthiness of SoCs used in diverse applications. This paper presents an overview of the various security challenges in the SoC design cycle and possible solutions for protection

Power Analysis Side Channel Attacks and Countermeasures for the Internet of Things

With the explosion in the number of internet of things (IoT) devices in recent years, the security of these devices has become an area of major concerns across the globe. Encryption is an essential means of protecting data in IoT devices, but cryptographic implementations are vulnerable to attacks as well. These vulnerabilities can allow attackers to completely bypass or significantly weaken the theoretical strength of the encryption algorithms. Resistance to cryptanalysis alone is not adequate for building a secure cryptosystem in practice. Power analysis side-channel attacks have emerged as a very effective method of discovering cryptographic keys by monitoring the power consumption of devices. Power consumption of the chips can reveal information about the cryptographic operations being performed or the data being processed. Numerous countermeasures against power analysis attacks have been discussed in the literature. However, all these countermeasures introduce various tradeoffs, such as increased power consumption, decreased performance, and increased space requirements for additional hardware. In addition to strong resistance to power analysis attacks and simplicity of implementation, developers need to evaluate the countermeasures by taking into consideration these tradeoffs while designing and implementing the IoT, which are often operated in heterogenous and highly resource constraint environments. This paper explores the state-of-the art power analysis attacks and their countermeasures and analyze the limitations of these countermeasures based on the constraints present in IoT devices

Hardware Trojan Attacks in FPGA Devices: Threat Analysis and Effective Counter Measures

Reconfigurable hardware including Field programmable gate arrays (FPGAs) are being used in a wide range of embedded applications including signal processing, multimedia, and security. FPGA device production is often outsourced to off-shore facilities for economic reasons. This opens up the opportunities for insertion of malicious design alterations in the foundry, referred to as hardware Trojan attacks, to cause logical and physical malfunction. The vulnerability of these devices to hardware attacks raises security concerns regarding hardware and design assurance. In this paper, we analyze hardware Trojan attacks in FPGA considering diverse activation and payload characteristics and derive a taxonomy of Trojan attacks in FPGA. To our knowledge, this is the first effort to analyze Trojan threats in FPGA hardware. Next, we propose a novel redundancy-based protection approach based on Trojan tolerance that modifies the application mapping process to provide high-level of protection against Trojans of varying forms and sizes. We show that the proposed approach incurs significantly higher security at lower overhead than conventional fault-tolerance schemes by exploiting the nature of Trojans and reconfiguration of FPGA resources

Spatio-temporal Pattern Discovery in Sensor Data: A Multivalued Decision Systems Approach

Discovering novel and interesting spatio-temporal patterns in sensor data is a major challenge in many scientific domains. Such data are often continuous, unbounded, and associated with high speed, time-variant distribution with local and spatial trends. This paper presents a formalism that includes an extension of classical rough set inference mechanism to reason with space-time variant data streams. The concept of multivalued decision systems has been used to account for multiple patterns in a single time window or snapshot. Such patterns or templates are incorporated in rough set-based rule induction process. A framework for sensor data integration is illustrated by using a space-time clustering mechanism followed by the generation of templates and local rules from such clusters. The multivalued decision system allows mining complex multiple patterns instead of a single value in a given template without requiring complex feature transformation. It also allows us to quantify and estimate potential data compression and associated uncertainty parameters. Finally, the results are validated and compared with other related algorithms. In general, the framework will help us understand the underlying reasoning mechanism about the “part and whole” or spatio-temporal mereological relationship without sacrificing the semantics of the sensor data attributes

Hardware Trojan Attacks in FPGA Devices: Threat Analysis and Effective Counter Measures

Reconfigurable hardware including Field programmable gate arrays (FPGAs) are being used in a wide range of embedded applications including signal processing, multimedia, and security. FPGA device production is often outsourced to off-shore facilities for economic reasons. This opens up the opportunities for insertion of malicious design alterations in the foundry, referred to as hardware Trojan attacks, to cause logical and physical malfunction. The vulnerability of these devices to hardware attacks raises security concerns regarding hardware and design assurance. In this paper, we analyze hardware Trojan attacks in FPGA considering diverse activation and payload characteristics and derive a taxonomy of Trojan attacks in FPGA. To our knowledge, this is the first effort to analyze Trojan threats in FPGA hardware. Next, we propose a novel redundancy-based protection approach based on Trojan tolerance that modifies the application mapping process to provide high-level of protection against Trojans of varying forms and sizes. We show that the proposed approach incurs significantly higher security at lower overhead than conventional fault-tolerance schemes by exploiting the nature of Trojans and reconfiguration of FPGA resources

Design and Validation for FPGA Trust under Hardware Trojan Attacks

Field programmable gate arrays (FPGAs) are being increasingly used in a wide range of critical applications, including industrial, automotive, medical, and military systems. Since FPGA vendors are typically fabless, it is more economical to outsource device production to off-shore facilities. This introduces many opportunities for the insertion of malicious alterations of FPGA devices in the foundry, referred to as hardware Trojan attacks, that can cause logical and physical malfunctions during field operation. The vulnerability of these devices to hardware attacks raises serious security concerns regarding hardware and design assurance. In this paper, we present a taxonomy of FPGA-specific hardware Trojan attacks based on activation and payload characteristics along with Trojan models that can be inserted by an attacker. We also present an efficient Trojan detection method for FPGA based on a combined approach of logic-testing and side-channel analysis. Finally, we propose a novel design approach, referred to as Adapted Triple Modular Redundancy (ATMR), to reliably protect against Trojan circuits of varying forms in FPGA devices. We compare ATMR with the conventional TMR approach. The results demonstrate the advantages of ATMR over TMR with respect to power overhead, while maintaining the same or higher level of security and performances as TMR. Further improvement in overhead associated with ATMR is achieved by exploiting reconfiguration and time-sharing of resources